I. Field of the Disclosure
The technology of the disclosure relates generally to pipelining posted write transactions over bus interconnects in processor-based computer systems.
II. Background
Modern processor-based computer systems, such as those containing Peripheral Component Interconnect (PCI)-based interconnects, often include one or more peripheral devices that may issue and/or receive a series of write transactions. Such devices may be generally characterized as belonging to a “strongly ordered” domain or a “weakly ordered” domain. Devices in a strongly ordered domain operate under a specification providing that an ordering relationship is maintained among all write transactions. The ordering relationship provides that the order in which the write transactions are completed at a consumer device is the same as the order in which the write transactions were sent by a producer device. In contrast, a series of write transactions in a weakly ordered domain do not have any inherent order (absent a special circumstance, such as an address overlap between two transactions). Thus, in a weakly ordered domain, the order in which the write transactions in the series arrive at a consumer device is not necessarily the same as the order in which the write transactions were sent.
When a producer device in a strongly ordered domain (i.e., a “strongly ordered device”) sends a series of write transactions to a consumer device in a weakly ordered domain (i.e., a “weakly ordered domain”), it is important that all write transactions are seen by the consumer device before the consumer device is notified that the series of write transactions are ready for consumption. However, because the order of arrival of the write transactions is not guaranteed in a weakly ordered domain, the write transactions may be seen by the consumer device out of their original order, which may be problematic in some circumstances. For example, a consumer device may receive a notification that the write transactions are ready for consumption before all write transactions in the series have been completed. This may result in system instability due to incomplete or corrupted data. Accordingly, a mechanism for providing a serialized ordering relationship for the write transactions as they pass to the weakly ordered domain is necessary.
One approach known in the art addresses this requirement by issuing write transactions one at a time, and waiting for completion of a previous write transaction before sending out a next write transaction. However, this approach may result in unacceptably long data transfer times, which may negatively affect system performance. Another known approach provides a centralized system arbiter configured to provide pipelining of write transactions by detecting a retry of a write transaction, and further configured to retry all subsequent write transactions. Under some approaches, a centralized system arbiter may itself be responsible for re-issuing write transactions in order on behalf of the receiving device. While the centralized system arbiter may ensure a serialized ordering relationship among the write transactions, it may not scale well in larger computer systems requiring multiple distributed arbiters that may need to communicate synchronously.